Design and implementation of an adaptive code discriminator in a DSP/FPGA-based Galileo receiver |
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| Authors: | Jyh-Ching Juang Yu-Hsuan Chen Tsai-Ling Kao Yung-Fu Tsai |
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| Institution: | (1) Department of Electrical Engineering, National Cheng Kung University, No. 1, University Road, Tainan, Taiwan |
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| Abstract: | In the design of a global navigation satellite system receiver, the tracking performance depends on the code tracking loop
and the associated discriminator. An adaptive code discriminator under a multi-correlator architecture has been designed based
on a multi-objective principle to achieve a balance among various, sometimes conflicting, design objectives. With the proposed
optimization approach and adaptive logic, concerns of large pull-in region and small steady-state error can be addressed.
The proposed scheme is implemented in a digital signal processor/field programmable gate array board and an experiment is
conducted to process GIOVE-A signals. The test results reveal the advantages of the proposed code tracking architecture and
discriminator design. |
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