| 基于FPGA的高动态P码直捕算法设计与实现 |
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| 引用本文： | 吴华兵,胡永辉,何在民,王康.基于FPGA的高动态P码直捕算法设计与实现[J].全球定位系统,2010,35(6):7-11. |
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| 作者姓名： | 吴华兵 胡永辉 何在民 王康 |
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| 作者单位： | [1]中国科学院国家授时中心,陕西西安710600 [2]中国科学院精密导航定位与定时技术重点实验室,陕西西安710600 [3]中国科学院研究生院,北京100039 |
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| 基金项目： | 武汉大学卫星导航与定位教育部重点实验室青年基金项目资助 |
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| 摘 要： | 长周期精密测距码（P码）的直接捕获技术对提高导航接收机的性能十分关键,为了设计出高动态、低信噪比环境下的P码快速直接捕获接收机,采用部分匹配滤波器组实现伪码时域并行搜索,结合小点数的快速傅里叶变换（FFT）,将匹配滤波器输出的部分相关值进行功率谱分析,完成多普勒频率偏移的并行搜索。硬件实现时结合FPGA的特殊结构,提高资源利用率,同时采用并行流水机制处理ADC的采样信号,对于每一个采样点,均可以在下一个采样点到达之前完成该点的码相位和频率的二维搜索。对比国内外P码接收机的研究成果,算法在捕获时间上有很大改进。在信号功率为-165 dBW,伪码相位±1 s的时间不确定度,以及多普勒频率偏移±16 kHz的条件下,捕获时间小于10 s,完全适用于高动态环境下的P码快速直接捕获。
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| 关 键 词： | 高动态 P码直捕 匹配滤波器组 FFT FPGA实现 |
Design and Implementation of High Dynamic P Code Direct Acquisition based on FPGA |
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| WU Hua-bing,HU Yong-hui,HE Zai-min,WANG Kang.Design and Implementation of High Dynamic P Code Direct Acquisition based on FPGA[J].Gnss World of China,2010,35(6):7-11. |
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| Authors: | WU Hua-bing HU Yong-hui HE Zai-min WANG Kang |
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| Institution: | 1.National Time Service Center,Chinese Academy of Sciences,Xi＇an Shaanxi 710600,China;2.Key Laboratory for Precise Navigation,Positioning and Timing of Chinese Academy of Sciences,Xi＇an Shaanxi 710600,China;3.Graduate University of Chinese Academy of Sciences,Beijing 100039,China) |
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| Abstract: | The technique of long period precise ranging code（P code） direct acquisition is extremely important for enhancing the performance of navigation receiver.To design a receiver possessed P code direct acquisition in high dynamic environment,low-SNR,our method is that the partial matched filter（PMF） bank is used for pseudo-code phase parallel search in time domain,and the power spectrum analysis to the related signals outputted from the PMF bank is performed by using the little point fast Fourier transform（FFT）,so the Doppler frequency offset parallel search in frequency domain has been finished.The hardware implementation combines with the special structures of the Field Programmable Gate Array（FPGA）.The digital IF sampling signals of ADC can be processed in parallel pipelining scheme,for every sampling point the two-dimension search of the code phase and frequency can be finished before the next point is coming.Compared with domestic and foreign methods of P code acquisition,the acquisition time can be extremely reduced.The acquisition time is less than 10 s as the power of received signals is-165 dBW,the uncertainty of code phase is ±1 s,and the Doppler frequency offset is about ±16 kHz.It will be fully applicable to the direct acquisition receiver in high dynamic environment. |
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| Keywords: | High dynamic P code direct acquisition matched filter bank FFT FPGA implementation |
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